我使用IAR5.4平台 移植UCOS-II+UCGUI调试问题分析，需要移植代码的请加我QQ：270540273, 共同分析问题
OS及GUI我在STM32F103ZE中调试OK
现有4个任务：
1. LCD显示
2.GUI
3.LED
4.USART
1. 移植OS成功，在代码量小时各任务运行正常， 但出现调试警告：
Thu Mar 17 10:01:15 2011: The stack pointer for stack 'SVC_STACK' (currently 0x302A9380) is outside the stack range (0x30200000 to 0x30200200)
按警告我把'SVC_STACK' 加大无效果，
当我把UCGUI编译进去，程序运行不正常，从原因来看 在程序中各个CONST的指针数据初始化不正确，
应该在系统运行的各变量与SVC_STACK堆栈区重合，把全局变量及常量指针数据覆盖了。造成程序不能正常运行；
现寻求解决办法？请高手指点，如何将系统运行的变量区域与各常量指针 与SVC_SATCK区域分隔开来？以下是启动代码：
。S文件
;Filename: startup.s
;By
zhnyang@21cn.com;@2009-4-4
;For S3C2410A(Run after Reset)
;Copyright Reserved
;Note: @Little Endian
;##########################################################
; Watchdog Timer Definitions
;----------------------------------------------------------
WT_BASE EQU 0x53000000 ;Watchdog Base Address
WTCON_OFS EQU 0x00
WTDAT_OFS EQU 0x04
WTCNT_OFS EQU 0x08
WTCON_Val EQU 0x00007C18
WTDAT_Val EQU 0x00007530
;----------------------------------------------------------
; Clock Management Definitions
;----------------------------------------------------------
CLK_BASE EQU 0x4C000000 ;Clock Base Address
LOCKTIME_OFS EQU 0x00
MPLLCON_OFS EQU 0x04
UPLLCON_OFS EQU 0x08
CLKCON_OFS EQU 0x0C
CLKSLOW_OFS EQU 0x10
CLKDIVN_OFS EQU 0x14
CAMDIVN_OFS EQU 0x18
LOCKTIME_Val EQU 0x00FFFFFF
MPLLCON_Val EQU 0x0007F021 ;FCLK=7F021=405MHz FCLK=7D011=532MHz
UPLLCON_Val EQU 0x00038022 ;UCLK=48MHz
CLKCON_Val EQU 0x0007FFF0
CLKSLOW_Val EQU 0x00000004
CLKDIVN_Val EQU 0x00000005 ;HCLK=FCLK/6= 88.66MHZ PCLK=HCLK/2=44.33MHZ
CAMDIVN_Val EQU 0x00000000 ;CLKDIVN[2:1]=11 HCLK=FCLK/6
;----------------------------------------------------------
; Memory Controller Definitions
;----------------------------------------------------------
MC_BASE EQU 0x48000000 ;Memory Controller Base Address
BWSCON_Val EQU 0x22111110 ;32-bit data bus
BANKCON0_Val EQU 0x00007FFC
BANKCON1_Val EQU 0x00007FFC
BANKCON2_Val EQU 0x00000700
BANKCON3_Val EQU 0x00000700
BANKCON4_Val EQU 0x00002E50
BANKCON5_Val EQU 0x00002E50
BANKCON6_Val EQU 0x00018005
BANKCON7_Val EQU 0x00018005
REFRESH_Val EQU 0x00A804F5
BANKSIZE_Val EQU 0x000000B1 ;64MB
MRSRB6_Val EQU 0x00000030
MRSRB7_Val EQU 0x00000030
;----------------------------------------------------------
; Some ARM920T CPSR bit discriptions
;----------------------------------------------------------
ModeUSR EQU 0x10
ModeFIQ EQU 0x11
ModeIRQ EQU 0x12
ModeSVC EQU 0x13
ModeABT EQU 0x17
ModeUND EQU 0x1B
ModeSYS EQU 0x1F
I_Bit DEFINE 0x80 ;I=1,Disable IRQ
F_Bit DEFINE 0x40 ;F=1,Disable FIQ
;----------------------------------------------------------
MODULE startup
SECTION CSTACK:DATA:NOROOT(3)
SECTION SVC_STACK:DATA:NOROOT(3)
SECTION IRQ_STACK:DATA:NOROOT(3)
SECTION FIQ_STACK:DATA:NOROOT(3)
SECTION UND_STACK:DATA:NOROOT(3)
SECTION ABT_STACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
PUBLIC __iar_program_start ;Must use this label
ARM
__vectors: ;0~0x3F, 16 Entries
LDR PC,=start_up ;RESET
NOP ;Undef
NOP ;SWI
NOP ;PAbt
NOP ;DAbt
NOP ;
NOP ;IRQ
NOP ;FIQ
start_up DCD __iar_program_start
DS32 7
SECTION .text:CODE:NOROOT(2)
IMPORT main
ARM
;Memory Controller Configuration
MC_CFG DCD BWSCON_Val
DCD BANKCON0_Val
DCD BANKCON1_Val
DCD BANKCON2_Val
DCD BANKCON3_Val
DCD BANKCON4_Val
DCD BANKCON5_Val
DCD BANKCON6_Val
DCD BANKCON7_Val
DCD REFRESH_Val
DCD BANKSIZE_Val
DCD MRSRB6_Val
DCD MRSRB7_Val
;Clock Management Configuration
CLK_CFG DCD LOCKTIME_Val
DCD CLKDIVN_Val
DCD MPLLCON_Val
DCD UPLLCON_Val
DCD CLKSLOW_Val
DCD CLKCON_Val
DCD CAMDIVN_Val
__iar_program_start: ;Run after Power ON RESETog Timer
;Disable the Reset Function of Watchd
LDR R0,=WT_BASE
LDR R1,=WTCON_Val
LDR R2,=WTDAT_Val
STR R2,[R0,#WTCNT_OFS]
STR R2,[R0,#WTDAT_OFS]
STR R1,[R0,#WTCON_OFS] ;0.1Hz(10s)
;Set CPU Clock(405MHz),PCLK=405/8MHz
LDR R0,=CLK_BASE
ADR R8,CLK_CFG
LDMIA R8,{R1-R7}
STR R1,[R0,#LOCKTIME_OFS]
STR R2,[R0,#CLKDIVN_OFS]
STR R3,[R0,#MPLLCON_OFS]
STR R4,[R0,#UPLLCON_OFS]
STR R5,[R0,#CLKSLOW_OFS]
STR R6,[R0,#CLKCON_OFS]
STR R7,[R0,#CAMDIVN_OFS]
MRC p15,0,R0,c1,c0,0
ORR R0,R0,#0xC0000000
MCR p15,0,R0,c1,c0,0
;Config Memory(0x3000 0000, 32MB, Bank 6)
ADR R14,MC_CFG
LDMIA R14,{R0-R12}
LDR R14,=MC_BASE
STMIA R14,{R0-R12}
;Setup Stack for Each Mode
;Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #ModeUND | I_Bit | F_Bit
LDR SP,=SFE(UND_STACK)
;Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #ModeABT | I_Bit | F_Bit
LDR SP,=SFE(ABT_STACK)
;Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #ModeFIQ | I_Bit | F_Bit
LDR SP,=SFE(FIQ_STACK)
;Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #ModeIRQ | I_Bit | F_Bit
LDR SP,=SFE(IRQ_STACK)
;Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #ModeSVC | I_Bit | F_Bit
LDR SP,=SFE(SVC_STACK)
;Enter System Mode and set its Stack Pointer
; MSR CPSR_c, #modeSYS
; LDR SP,=SFE(CSTACK)
;Enter the C Code
LDR R0,=main
BX R0
END
以下是ICF文件：
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x30000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x30000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x301FFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x30200000;
define symbol __ICFEDIT_region_RAM_end__ = 0x32000000;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x200;
define symbol __ICFEDIT_size_svcstack__ = 0x200;
define symbol __ICFEDIT_size_irqstack__ = 0x100;
define symbol __ICFEDIT_size_fiqstack__ = 0x200;
define symbol __ICFEDIT_size_undstack__ = 0x100;
define symbol __ICFEDIT_size_abtstack__ = 0x100;
define symbol __ICFEDIT_size_heap__ = 0x80000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP };
以下是JILNK下载代码前初始化SDRAM文件
setup()
{
__writeMemory32(0x00000000, 0x53000000, "Memory"); /*watchdog timer disable */
__writeMemory32(0xffffffff, 0x4a000008, "Memory"); /* disable all interrupts */
__writeMemory32(0x000007ff, 0x4a00001c, "Memory"); /* disable all sub-interrupts */
__writeMemory32(0xffffffff, 0x4a000000, "Memory"); /* clear all source pending bits */
__writeMemory32(0x000007ff, 0x4a000018, "Memory"); /* clear all sub-source pending bits */
__writeMemory32(0xffffffff, 0x4a000010, "Memory"); /* clear interrupt pending bit */
__writeMemory32(0x00000003, 0x4c000014, "Memory"); /* FCLK:HCLK:PCLK = 1:2:4*/
__writeMemory32(0x00ffffff, 0x4c000000, "Memory"); /* PLL locktime counter =300US*/
__writeMemory32(0x000ad022, 0x4c000004, "Memory"); /* Fin=12MHz FCLK=PLLOUT=271.5MHZ*/
__writeMemory32(0x22111110, 0x48000000, "Memory"); /* BWSCON */
__writeMemory32(0x00007FFC, 0x48000004, "Memory"); /* BANKCON0 */
__writeMemory32(0x00007FFC, 0x48000008, "Memory"); /* BANKCON1 */
__writeMemory32(0x00000700, 0x4800000c, "Memory"); /* BANKCON2 */
__writeMemory32(0x00000700, 0x48000010, "Memory"); /* BANKCON3 */
__writeMemory32(0x00002E50, 0x48000014, "Memory"); /* BANKCON4 */
__writeMemory32(0x00002E50, 0x48000018, "Memory"); /* BANKCON5 */
__writeMemory32(0x00018009, 0x4800001c, "Memory"); /* BANKCON6 */
__writeMemory32(0x00018009, 0x48000020, "Memory"); /* BANKCON7 */
__writeMemory32(0x00A804E9, 0x48000024, "Memory"); /* REFRESH */
__writeMemory32(0x000000b1, 0x48000028, "Memory"); /* BANKSIZE */
__writeMemory32(0x00000030, 0x4800002c, "Memory"); /* MRSRB6 */
__writeMemory32(0x00000030, 0x48000030, "Memory"); /* MRSRB7 */
}
execUserPreload()
{
__message "Initializing SDRAM ...\n";
setup();
__message "Initializing SDRAM ... Completed\n";
}
