主题 : VCLK输出的时钟频率不对 复制链接 | 浏览器收藏 | 打印
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楼主  发表于: 2015-09-09 04:57

 VCLK输出的时钟频率不对

图片:
[    0.423408] s3cfb s3cfb.0: src_clk=800000000, vclk=30240000, div=26(12), rate=66666666
[    0.423421] s3cfb s3cfb.0: fimd sclk rate 61538461, clkdiv 0xfffffc
[    0.423593] s3cfb s3cfb.0: [fb0] win2: dma: 0x60ad8000, cpu: 0xe4879000, size: 0x00465000
[    0.425527] Start display and show logo
[    0.430030] s3cfb s3cfb.0: parent clock: 61538461, vclk: 30240000, vclk div: 2
[    0.565038] s3cfb s3cfb.0: registered successfully
[    0.565367] s3cfb_extdsp s3cfb_extdsp.0: registered successfully
[    0.565642] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    0.855215] s5pv210-uart.0: ttySAC0 at MMIO 0x13800000 (irq = 16) is a S3C6400/10
[    1.867369] console [ttySAC0] enabled
[    1.915056] s5pv210-uart.1: ttySAC1 at MMIO 0x13810000 (irq = 20) is a S3

根据附件中的设置 等到的乘积也是30240000


上面显示 vclk: 30240000 ,但是用示波器测量vclk的值是30.771MHz,Vsync引脚的值是61.5HZ,哪位大哥知道这是什么问题吗?