解决此问题的补丁如下，友善之臂 的工作人员 也可以参考这个修改下 supperboot 中的 DDR3控制器的配置。尽快发布个新版的supperboot.
diff -Naur uboot_tiny4412/board/samsung/tiny4412/mem_init_tiny4412.S uboot_tiny4412ok/board/samsung/tiny4412/mem_init_tiny4412.S
--- uboot_tiny4412/board/samsung/tiny4412/mem_init_tiny4412.S 2013-07-29 18:08:00.000000000 +0800
+++ uboot_tiny4412ok/board/samsung/tiny4412/mem_init_tiny4412.S 2014-06-24 09:31:14.182259182 +0800
@@ -70,9 +70,9 @@
ldr r1, =0x00312640
str r1, [r0, #DMC_MEMCONTROL]
- ldr r1, =0x40e01323
+ ldr r1, =0x40801333
str r1, [r0, #DMC_MEMCONFIG0]
- ldr r1, =0x60e01323
+ ldr r1, =0x80801333
str r1, [r0, #DMC_MEMCONFIG1]
#ifdef CONFIG_IV_SIZE
@@ -97,7 +97,7 @@
str r1, [r0, #DMC_TIMINGPOWER]
#endif
#ifdef MCLK_400
- ldr r1, =0x4046654f
+ ldr r1, =0x6946654f
str r1, [r0, #DMC_TIMINGROW] @TimingRow
ldr r1, =0x46400506
str r1, [r0, #DMC_TIMINGDATA] @TimingData
@@ -212,9 +212,9 @@
ldr r1, =0x00312640
str r1, [r0, #DMC_MEMCONTROL]
- ldr r1, =0x40e01323 @Interleaved?
+ ldr r1, =0x40801333 @Interleaved?
str r1, [r0, #DMC_MEMCONFIG0]
- ldr r1, =0x60e01323
+ ldr r1, =0x80801333
str r1, [r0, #DMC_MEMCONFIG1]
#ifdef CONFIG_IV_SIZE
@@ -239,7 +239,7 @@
str r1, [r0, #DMC_TIMINGPOWER]
#endif
#ifdef MCLK_400
- ldr r1, =0x4046654f
+ ldr r1, =0x6946654f
str r1, [r0, #DMC_TIMINGROW] @TimingRow
ldr r1, =0x46400506
str r1, [r0, #DMC_TIMINGDATA] @TimingData
diff -Naur uboot_tiny4412/board/samsung/tiny4412/tiny4412.c uboot_tiny4412ok/board/samsung/tiny4412/tiny4412.c
--- uboot_tiny4412/board/samsung/tiny4412/tiny4412.c 2013-07-29 13:02:42.000000000 +0800
+++ uboot_tiny4412ok/board/samsung/tiny4412/tiny4412.c 2014-06-23 16:17:41.480604224 +0800
@@ -195,6 +195,14 @@
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+ gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
+ gd->bd->bi_dram[4].size = PHYS_SDRAM_5_SIZE;
+ gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
+ gd->bd->bi_dram[5].size = PHYS_SDRAM_6_SIZE;
+ gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
+ gd->bd->bi_dram[6].size = PHYS_SDRAM_7_SIZE;
+ gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
+ gd->bd->bi_dram[7].size = PHYS_SDRAM_8_SIZE;
#ifdef CONFIG_TRUSTZONE
gd->bd->bi_dram[nr_dram_banks - 1].size -= CONFIG_TRUSTZONE_RESERVED_DRAM;
diff -Naur uboot_tiny4412/include/configs/tiny4412.h uboot_tiny4412ok/include/configs/tiny4412.h
--- uboot_tiny4412/include/configs/tiny4412.h 2013-07-29 14:29:52.000000000 +0800
+++ uboot_tiny4412ok/include/configs/tiny4412.h 2014-06-24 09:37:22.378253848 +0800
@@ -74,9 +74,9 @@
/* APLL : 1.3GHz */
//#define CONFIG_CLK_ARM_1200_APLL_1300
/* APLL : 1.4GHz */
-#define CONFIG_CLK_ARM_1200_APLL_1400
+//#define CONFIG_CLK_ARM_1200_APLL_1400
/* APLL : 1.5GHz */
-//#define CONFIG_CLK_ARM_1500_APLL_1500
+#define CONFIG_CLK_ARM_1500_APLL_1500
/* bus clock: 100Mhz, DMC clock 200Mhz */
//#define CONFIG_CLK_BUS_DMC_100_200
@@ -278,7 +278,7 @@
#ifdef CONFIG_EVT0_STABLE
#define CONFIG_NR_DRAM_BANKS 2
#else
-#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_NR_DRAM_BANKS 8
#endif
#define SDRAM_BANK_SIZE 0x10000000 /* 256 MB */
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
@@ -407,6 +407,7 @@
/*
* Ethernet Contoller driver
*/
+#define CONFIG_CMD_NET
#ifdef CONFIG_CMD_NET
#define CONFIG_NET_MULTI
